Ternary solder for the enhancement of C-4 fatigue life

ABSTRACT

An enhanced fatigue life solder comprising, by weight, about 1-3% tin, about 1-3% silver and the balance essentially lead is provided. The solder is particularly useful for joining electronic components and in particular for making C-4 interconnections. A method for using the solder to make electronic components and electric components made using the method are also provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to solder having enhanced fatigue life propertiesand, more particularly, to the use of the solder to make C-4 connectionsin electronic components. The solder also exhibits a low standarddeviation (sigma) with regard to the connection failure distributionthus delaying the use time for earliest failure of a solder joint.

2. Description of Related Art

The use of solder to join materials such as components of an electronicstructure is well known in the art. In the electronics area, there are amyriad of structures which require connection to other similarstructures or to other levels of packaging. Examples include mounting ofintegrated circuit chips to a metallized substrate; mounting a card onwhich several chips could be mounted to a board which providesinterconnection circuitry, etc. For the sake of clarity and consistencyin describing the present invention the specification will be directedto electronic components made using Controlled Collapse Chip Connection(C-4) technology.

C-4 technology is an interconnection technology developed by IBM as analternative Lo wire bonding. Broadly stated, one or more integratedcircuit chips are mounted above a single or multilayer substrate andpads on the chip are electrically connected to corresponding pads on thesubstrate by a plurality of electrical connections known as solderbumps. An example: of an area array C-4 configuration is a square gridarray which is 11 C-4 pads long by 11 pads wide on 10 mil centers. Afive mil solder bump is located at every intersection in the grid exceptone which is typically displaced for orientation purposes. A popularchip is a circuit "computer-on-a-chip" which has 762 C-4 solder bumps ina 29×29 area array.

The C-4 technology has also extended to other applications and is nowused on thin-film resistor and composite chips in hybrid modularapplications. Solder pads for this application are very large-about 25mil in diameter. At the other extreme, C-4s have been used for precisionregistration and alignment in the joining of a GaAs wave guide. The mostdense area array reported has been a 128×128 array of 1 mil bumps onabout 2 mil centers resulting in 16,000 pads.

The C-4 technology utilizes solder bumps deposited on wetable metalterminals on the chip and a matching foot print of solder wetableterminals on the substrate. The upside-down chip (flip chip) is alignedto the substrate, and all joints are made simultaneously by reflowingthe solder bumps. The flow on the chip is limited by a ball limitingmetallurgy (BLM) pad which is generally a circular pad of evaporated,thin-film metal such as chromium, copper and gold that provides thesealing of the via as well as the solderable, conductive base for thesolder bump. A very thick deposit of evaporated solder acts as theprimary conduction and joining material between chip and substrate.

Melting point has been a consideration in the choice of solder alloysfor C-4s. Lead solders, especially 95 Pb/5 Sn have been widely used withalumina ceramic substrates because of their high melting point ofapproximately 315° C. Their use for the chip connection allows otherlower-melting point solders to be used at the module-to-card orcard-to-board packaging level without remelting the chip's C-4s.Intermediate melting point solders such as eutectic 63 Sn/37 Pb (meltingpoint 183° C.) and a 50 Pb/50In melting point of approximately 220° C.have been used. In "Microelectronics Packaging Handbook", edited by R.R. Tummala and Rymaszewski, 1989, van Nostrand Reinhold, pages 361-391,C-4 chip to package interconnections as well as typical solders used inC-4 technology are discussed and this reference is hereby incorporatedby reference.

While there are a number of technologies that can be used to form thepads and the solder bumps, metal mask technology is most widely used atthe present time. BLM and solder are evaporated through holes in a metalmask and deposited as an array of pads onto the wafer surface. A typicalmultilayer structure of the BLM can be described by using Cr--Cu--Au andan example. A typical evaporator would have numerous metal charges withthermal energy supplied by resistance, induction or electron beams. Cris evaporated first for adhesion to the passivation layer as well as toform a solder reaction barrier to the aluminum. A phased layer of Cr andCu are coevaporated next to provide resistance to multiple reflows. Thisis followed by a pure Cu layer to form the soluble metallurgy. A flashof gold is then provided as an oxidation protection layer. While leadand tin are usually in the same charge (single molten pool) the highervapor pressure component, Pb, deposits first, followed by tin on top ofthe lead. Reflow in a H₂ ambient furnace at about 350° C. melts andhomogenizes the pad and brings the solder bump to its spherical shape.Photolithographic processes and combinations of photolith and metal maskare becoming more and more popular for fabricating terminals.

Once the BLM, TSM (top surface metallurgy of the substrate to be joined)and solder are in place, the joining of chips to the substrate using C-4technology is relatively straight forward. Flux, either water-whiterosin for high-lead solders with water-soluble flux for low lead andother low-melting solders, is normally placed on the substrate as atemporary adhesive to hold the chips in place. Such an assembly is thensubjected to a reflow thermal cycle wherein the pads on the chip and thesubstrate self-align due to the high-surface-tension forces of thesolder to complete the assembly. Once the chip-joining operation iscomplete, cleaning of flux residues is accomplished with such solventsas chlorinated solvents or xylene. The assembly is then electricallytested.

As mentioned above, new technologies are continuously increasing thenumber of C-4 interconnections per device, and/or the size of the chip,both of which affect the stresses on the solder interconnections. Aschips become more and more dense, higher input/output counts will drivearea arrays of terminals to as many as 155,000 pads on a 20 mm chip.This will result as the number of pads increase while the pad sizes andspacings decrease. The new technologies will induce large strains to thesolder joint and new solders are needed to meet the fatigue requirementsof these types interconnections.

Bearing in mind the problems and deficiencies of the prior art, it istherefore an object of the present invention to provide a solder havingenhanced fatigue life properties.

It is another object of the present invention to provide a method formaking solder interconnections, especially C-4 interconnections, usingthe specially defined solder of the invention.

A further object of the invention is to provide electronic structures,especially C-4 containing structures, made using the method of theinvention.

Still other objects and advantages of the invention will in part beobvious and will in part be apparent from the specification.

SUMMARY OF THE INVENTION

The above and other objects, that will be apparent to those skilled inthe art, are achieved by the present invention which relates to anenhanced fatigue resistant solder useful for joining electroniccomponents comprising, by weight, about 1-3% tin, preferably about 1-2%tin, about 1-3% silver, preferably about 1-2% silver and the balanceessentially lead. Preferably, the solder contains tin in the amount ofabout 1.25%-1.75%, and more preferably about 1.4%-1.6% e.g., 1.5% andsilver in an amount of about 1.25%-1.75% and more preferably about1.4%-1.6%, e.g., 1.5%.

In another aspect of the present invention, a method is provided formaking solder electrical interconnections, especially C-4interconnections, in an electronic component comprising the steps of:

applying the solder to one surface of a first substrate of theelectronic component, the solder comprising, by weight, about 1-3% tin,preferably about 1-2% tin, about 1-3% silver, preferably about 1-2%silver and the balance essential lead;

bringing the surface of a second substrate of the electronic componentto be joined to the first substrate into contact with the solder; and

heating the contacted substrates to a temperature sufficient to form thesolder interconnections between the substrates.

In a further aspect of the invention, the electronic components to bejoined are a multilayer ceramic substrate and a semiconductor chip.

In a further aspect of the invention, electronic components made by theabove methods are also provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention believed to be novel and the elementscharacteristic of the invention are set forth with particularity in theappended claims. The figures are for illustration purposes only and arenot drawn to scale. The invention itself, however, both as toorganization and method of operation, may best be understood byreference to the detailed description which follows taken in conjunctionwith the accompanying drawings in which:

FIG. 1 is a log-normal graph showing the relationship between cycles tofailure and the cumulative percent failure on a C-4 basis for the alloyof the invention vs. alloys of the prior art.

FIG. 2 is a log-normal graph showing the relationship between the cyclesto failure and the cumulative percent fail on a C-4 basis for C-4 jointsin a 17 by 17 footprint chip for the alloy of the invention and alloysof the prior art.

FIG. 3 is a log-linear graph showing the relationship between thecumulative percent fails per chip and field cycles for the alloy of theinvention and an alloy of the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In describing the preferred embodiment of the present invention,reference will be made herein to FIGS. 1-3 of the drawings in which likenumerals refer to like features of the invention. Features of theinvention are not necessarily shown to scale in the drawings.

The solder of the invention comprises, by weight, about 1-3% silver,preferably about 1-2% silver, about 1-3% tin, preferably about 1-2% tinand the balance essentially lead including the usual impurities. Purelead is preferably used. It is most preferred to use alloys comprisingabout 1.25%-1.75% silver and about 1.25%-75% tin and the balanceessentially lead with a highly preferred solder comprising about1.4%-1.6% silver, about 1.4%-1.6% tin and the balance essentially lead.A specific alloy which is preferred because of its demonstratedeffectiveness is a solder containing about 1.5% tin, about 1.5% silverand the balance lead.

The alloy of the invention may be formed by melting the componentstogether and cooling the mixture to form the solder in solid form. Inthe solid form, the alloy has a homogeneous structure containing finelydivided Ag₃ Sn precipitates distributed throughout the matrix asdetermined by electron diffraction analysis. The precipitates aregenerally in the shape of platelets with dimensions of the order of 100nm in thickness and 250 nm in diameter as determined by electronmicroscopy. The silver is found to be totally consumed or reacted informing the Ag₃ Sn phase, and the silver reaction and homogeneousdistribution of the Ag₃ Sn precipitate phase is considered to occurrelatively fast so that on solidification no free silver remains in thesolidified solder. The remainder of the tin remains in solution with thelead.

When the alloy is in the molten state each of the silver, tin and leadis present in its elemental form. The alloy of the invention istypically applied to the pad of the electronic component to be joinedfrom the molten state by commonly used evaporation techniques. Theevaporation is typically accomplished through a molybdenum mask from asingle metal charge of the alloy but the three metals can also be platedonto the pad surface. After evaporation, the three metals are found tobe stratified forming a lead layer on the pad surface, an intermediatetin layer and an overlying silver layer. These layers form due to therelative vapor pressures of the elements. When the solder is reflowed atan elevated temperature such as 350° C. the ternary alloy is formed witha homogenous structure containing finely divided Ag₃ Sn precipitates andthe solder forms a hemispherical shape. Some intermetallic componentsmay be formed as a result of the reflow process with the elementsreacting with the metallization on the pad surface. The intermetalliccomponents adhere to the metallized surface but traces of theintermetallic may dissolve in the solder matrix. For example, if copperand gold are in the pad metallization a copper tin and/or gold tinintermetallic component may form. Also, other metallic elements such asnickel may also form a nickel-tin intermetallic and be present in thesolder phase. These intermetallic components have not been found to haveany significant effect on the properties, e.g., fatigue of the solderjoint. It will be appreciated however, that due to the reflow andjoining operation that the originally evaporated ternary alloy usuallybecomes a more complex alloy depending on the elements present on themetallized pads.

It has been found that using the solder of the invention providessoldered joints such as C-4 joints to have an extended fatigue lifecompared to solder joints made with solder of the prior art. The fatigueenhancement in terms of fatigue life at the tolerance fail level isgenerally more than two to three times the prior art alloys which arecommonly used to make solder joints. Another considerable benefit whichis provided by using the solder of the invention is the low sigma value(standard deviation of the fail times). This means that a first C-4 failinstead of occurring, say, after 2000 cycles will occur beyond 6000cycles with it being appreciated that one C-4 failure is all that istypically needed to exceed technology tolerance limits. Therefore, thetightness (low value) of the sigma limit is an extremely importantfactor in minimizing failures of electronic components. It ishypothesized that the Ag₃ Sn precipitates serve as nucleating sitesduring solder solidification controlling the grain size structure of thesolder and act as obstacles to crack propagation which israte-controlling in the fail mechanism. The Ag₃ Sn precipitatesconsiderably slow down crack progation in the solder joint resulting inalso a tight sigma limit.

Another benefit of the solder of the invention is that none of the otherrequired properties of the solder are negatively effected such ascorrosion, metal migration, electromigration, etc. The fine precipitatescoupled with more grain boundaries make propagation of a fault much moredifficult such that their fatigue fails will converge within a tightdistribution with a minimum scatter. The concentration of theprecipitates in the C-4 solder bump is estimated at about 2% by weighton the basis of a fully reactive silver and tin components.

The solder of the invention and a lead-3% tin control solder of theprior art were also tested for metal migration under water by biasingchip C-4s under various voltages. In both solders, the metal thatmigrated was lead. This test by water-drop for water-immersing isgenerally used in the electronic industry to determine which metal wouldbe susceptible or have the propensity Lo migrate under the worstpossible conditions. The results indicate that if any metal migrationwould even occur due to extreme conditions of water condensation intodefects or process residues would only be lead migration. These resultsconfirm that metal migration of alloy elements, i.e., silver and tin isnot expected or possible in the compound form or in solid solution withthe matrix or in small amounts as fine discrete phases. The electronmicroprobe analysis of the dendrites showed no trace of either silver ortin. In any case, metal migration test and T/H (temperature/humidity)under electric bias were conducted with TCM's (Thermal ConductionModule) under conditions of 85° C./80% RH (relative humidity) andapplied potential of 5 volts. The results of ternary and control arecomparable with the ternary having a slight advantage in the lowpercentile which in the region of interest.

Another benefit of the invention is that the extended fatigue life ofthe solder joints is attained both with and without the need for modulehermeticity and/or with and without an epoxy underfill. Sealing of themodule and/or the use of epoxy underfill is generally used to extend thelife of the component and the use of the ternary solder with itsenhanced fatigue life and low sigma properties obviates the need forsuch techniques to increase the life of the electronic component. Ofcourse, if such techniques are employed using the solder of theinvention even more enhanced component life properties would beachieved.

EXAMPLES

The solder of the invention was evaluated with prior art lead solderscontaining 1% tin, 3% tin and 0.5% tin and a lead solder containing 0.2%tin and 2% bismuth. The solder was tested on a chip having a DNP(distance to neutral point) of about 6 mm.

The results of the evaluation are shown in FIG. 1 where is clearly shownthat the alloy of the invention has a significantly higher number ofcycles-to-failure as compared to the prior art alloys. Also, it is shownthat the sigma limit for the solder of the invention is must less thanthe other solders indicating a more useful solder.

Tests other than fatigue tests such as wetability tests, corrosion testsand metal migration show commercially satisfactory results for thesolder of the invention as compared to the prior art solders. Similarfatigue tests as for the above example were conducted on chips having aDNP from 60 to greater than 100 mil. A 4 point probe was used for C-4resistance measurement together with a fail criterion of 30 mohms. Theresistance measured is that of the C-4 only, excluding contactresistance or parts of the circuitry. The test was terminated at 30,000cycles when about 40% of all solder bumps monitored (highest DNP's) hadfailed. About 100 chips and about 6000 C-4's per alloy were tested withthe electric resistive measurements being repeated every 1,500 cycles.The results shown in FIG. 2 again establish the clear superiority of thesolder of the invention with regard to the number of cycles-to-failureand the low sigma limit.

The solder of the invention was evaluated with the prior art 3% tin leadsolder with respect to fatigue. 33 chips of each alloy were joined toeach of the substrates after storing the chips in nitrogen for 1000hours. The substrates were cycled from 0 to 100° C., 48 cycles per day,for 30,000 cycles. Four point resistance measurements were made atintervals of 1,500 cycles. The results are shown in FIG. 3 and show thatthe ternary solder has a fatigue life of more than double that of thelead-3% tin alloy. The sigma limit is also about half that of the binarycontrol. Corrosion tests in 85° C./81% RH for 5,000 hours showed thatthe ternary is at least as resistant to corrosion as the lead-3% tinsolder.

While the present invention has been particularly described, inconjunction with a specific preferred embodiment, it is evident thatmany alternatives, modifications and variations will be apparent tothose skilled in the art in light of the foregoing description. It istherefore contemplated that the appended claims will embrace any suchalternatives, modifications and variations as falling within the truescope and spirit of the present invention.

Thus, having described the invention, what is claimed is:
 1. An enhancedfatigue resistant solder useful for joining electronic componentscomprising, by weight, about 1-3% tin, about 1-3% silver and balancelead, wherein the solder contains Ag₃ Sn distributed throughout thesolder.
 2. The solder of claim 1 wherein the tin is about 1-2% and thesilver is about 1-2%.
 3. The solder of claim 2 wherein the tin is about1.25%-1.75% and the silver is about 1.25%-1.75%.
 4. The solder of claim3 wherein the tin is about 1.4%-1.6% and the silver is about 1.4%-1.6%.5. An enhanced fatigue resistant solder useful for joining electroniccomponents comprising, by weight, about 1-3% tin, about 1-3% silver andbalance lead wherein the solder is formed by melting the componentstogether to form a molten mixture and cooling the mixture to form asolid solder having a homogenous structure containing finely divided Ag₃Sn precipitates distributed in the solder structure.
 6. The solder ofclaim 5 wherein the Ag₃ Sn precipitates are in the form of platelets. 7.The solder of claim 5 wherein the silver in the solder is totallyreacted forming the Ag₃ Sn precipitates.
 8. The solder of claim 5wherein the silver, tin and lead are melted together and the solderapplied by evaporation to a substrate through a mask forming astratified layer on the substrate comprising a lead layer, anintermediate tin layer and an overlying silver layer, which layers, whenthe solder is reflowed at an elevated temperature, forms a ternary alloywith a homogenous structure containing finely divided Ag₃ Snprecipitates.